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LTC1840 Dual Fan Controller with 2-Wire Interface
FEATURES
s s s s s
DESCRIPTIO
s s s s s s s s
Two 8-Bit Current DACs DACs Guaranteed Monotonic Known IC State on Power-Up Serial Interface Watchdog Timer with Disable 2-Wire Serial Interface Compatible with I2CTM and SMBus 2 Programmable Fan Tachometer Interfaces 4 Programmable General Purpose I/Os Small 16-Pin SSOP Package Single 2.7V to 5.75V Supply Operation Fault Output Signal Status Register Fan Blasting Function Nine Addresses Using Two Programming Lines
The LTC(R)1840 is a fan controller with two 8-bit current output DACs, two tachometer interfaces, and four general purpose I/O (GPIO) pins. It operates from a single supply with a range of 2.7V to 5.75V. A current output DAC is used to control an external switching regulator, which controls the fan speed. A current output DAC and tachometer allow a controller to form a closed control loop on fan velocity. The GPIO pins can be used as digital inputs or open drain pull-down outputs. The part features a simple 2-wire I2C and SMBus compatible serial interface that allows communication between many devices. The interface includes a fault status register that reflects the state of the part and which can be polled to find the cause of a fault condition. Other operational characteristics of the part, such as DAC output currents, GPIO modes, and tachometer frequency, are also programmed through the serial interface. Two address pins provide nine possible device addresses. The BLAST pin is provided to force the DAC output currents to program the maximum regulator output voltages through a single pin and gate the operation of the serial access timer.
APPLICATIO S
s s s s
Servers Desktop Computers Power Supplies Cooling Systems
, LTC and LT are registered trademarks of Linear Technology Corporation. I2C is a trademark of Philips Electronics N.V.
TYPICAL APPLICATIO
3.3V 3.3V 10k FAULT TO MASTER SDA SCL VCC
Low Parts Count, High Efficiency Dual Fan Control
+
10F 12V 0.1F VIN GPI04 BLAST IDACOUTA SYSTEM RESET RUN/SS SENSE LTC1771 PGATE ITH RC1 10k CC1 220pF VFB CFB1 100pF MODE GND UPS5817 RSENSE1 0.05
+
CVIN1 22F RFB1A 75k
Si6447DQ L1 47H
LTC1840 3.3V
12V VIN RSENSE2 0.05
+
3.3V 130 LED2
CVIN2 22F
130 LED1
NC NC
A0 A1 GPI01 GPI02 GND
GPI03 IDACOUTB TACHB TACHA RC2 10k CC2 220pF
RUN/SS SENSE LTC1771 ITH PGATE VFB CFB2 100pF MODE GND
Si6447DQ L2 47H UPS5817
ADDRESS = 1110010 (8 OTHERS POSSIBLE)
U
3.3V DC FAN COUT1 150F 10k TACH OUT
U
U
+
RFB1B 28k
2-NMB 6820PL-04W-B29-D50 FANS 1.1A NOM AT 12V 3.3V RFB2A 75k RFB2B 28k DC FAN COUT2 150F 10k TACH OUT
+
1840 TA01
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1
LTC1840
ABSOLUTE
(Note 1)
AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW SCL 1 SDA 2 A1 3 A0 4 FAULT 5 GPIO1 6 GPIO2 7 GND 8 16 VCC 15 IDACOUTA 14 IDACOUTB 13 BLAST 12 TACHB 11 TACHA 10 GPIO4 9 GPIO3
VCC to GND .................................................... -0.3 to 6V A0, A1 ............................................. -0.3 to (VCC + 0.3V) IDACOUTA, IDACOUTB ............................. -0.3 to (VCC + 0.75V) All other pins ................................................. -0.3 to 6V Operating Temperature LTC1840C ............................................... 0C to 70C LTC1840I .............................................-40C to 85C Storage Temperature Range ..................-65C to 125C Lead Temperature (Soldering, 10 sec).................. 300C
ORDER PART NUMBER LTC1840CGN LTC1840IGN
GN PART MARKING 1840 1840I
GN PACKAGE 16-LEAD PLASTIC SSOP TJMAX = 125C, JA = 110C/W
Consult LTC marketing for parts specified with wider operating temperature ranges.
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3V
SYMBOL DACs n DNL INL ZSE Resolution Differential Nonlinearity Integral Nonlinearity Zero-Scale Error Output Voltage Rejection Output Voltage Rejection IDACOUTA(FS), IDACOUTB(FS) Power Supply VCC ICC VUVLO VUVHYS fOSC PSRR GPIO Performance IO VIL VIH VIHYST ILEAK Output Current Sink Digital Input Low Voltage Digital Input High Voltage Input Hysteresis Leakage VGPIOX = 0.7V, Internal Pull-Down Enabled Internal Pull-Down Disabled Internal Pull-Down Disabled (Note 2) Internal Pull-Down Disabled
q q q
ELECTRICAL CHARACTERISTICS
PARAMETER
CONDITIONS
MIN 8
TYP
MAX
UNITS Bits
VDACOUT = 1.1V, Guaranteed Monotonic VDACOUT = 1.1V VDACOUT = 1.1V 1.1V< VDACOUT < 3.75V VCC = 5.75V, 1.1V < VDACOUT < 6.5V Sinking VDACOUT = 1.1V
q
0.9 4 -0.2 0.1 2 1 2 97 95 2.7 400 500 103 105 5.75 600 750 2.69 160 53 0.5
Full-Scale Current
q
Positive Supply Voltage Supply Current UVLO/POR Voltage UVLO/POR Voltage Hysteresis Oscillator Frequency Supply Sensitivity 2.7V < VCC < 5.75V (Note 2) VCC = 3V, A0 and A1 Floating VCC = 5V, A0 and A1 Floating
q
q
2.1 20
2.4 90 50 0.1
Oscillator Performance
q
47
10 0.3VCC 0.7VCC 50 1
2
U
LSB LSB A LSB LSB A A V A A V mV kHz %/V mA V V mV A
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W
U
U
WW
W
LTC1840
The q denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VCC = 3V
SYMBOL VIH VIL VLTH ILEAK CIN Digital Output SDA VOL VOL VIH VIL ILEAK Digital Input BLAST VLTH VIHYST ILEAK VIH VIL IIN fI2C t BUF t hD, STA t su, STA t su, STO t hD, DAT t su, DAT t LOW t HIGH tf tr Logic Threshold Voltage Input Hysteresis Digital Input Leakage Input High Voltage Input Low Voltage Input Current I2C Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time after (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock, Data Fall Time Clock, Data Rise Time (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) Note 2: Guaranteed by design not subject to test. AX Shorted to GND or VCC, VCC = 5V (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 0 4.7 4 4.7 4 300 250 4.7 4.0 300 1000 Measured on BLAST Falling Edge (Note 2), Measured on Rising Edge VCC = 5V and 0V, VIN = GND to VCC
q q
ELECTRICAL CHARACTERISTICS
PARAMETER Digital Input High Voltage Digital Input Low Voltage Logic Threshold Voltage Digital Input Leakage Digital Input Capacitance Digital Output Low Voltage Digital Output Low Voltage Digital Input High Voltage Digital Input Low Voltage Digital Input Leakage
CONDITIONS
q q
MIN 1.4
TYP
MAX
UNITS V
Digital Inputs SCL, SDA 0.6 1 1 10
q
V V A pF V V V
(Note 2) VCC = 5V and 0V, VIN = GND to VCC (Note 2) IPULL-UP = 3mA IPULL-UP = 1mA
0.4 0.4 0.7VCC 0.3VCC 1 0.95 20 1 0.9VCC 0.1VCC 100 100 1.0 1.05
Digital Output FAULT
q
Digital Inputs TACHA, TACHB
q q
V A V mV A V V A kHz s s s s ns ns s s ns ns
VCC = 5V and 0V, VIN = GND to VCC
Address Inputs A0, A1
Timing Characteristics
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.
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LTC1840 TYPICAL PERFOR A CE CHARACTERISTICS
Supply Current vs Supply Voltage
550 TA = 25C
450 440 100.05 IDACOUT (A)
500
ICC (A)
ICC (A)
450
400 2.5
3.5
4.5 VCC (V)
5.5
IDACOUT FS vs VDACOUT at VCC = 3V to 5V
120 TA = 25C 100 80 60 40 20 0
IDACOUT (A)
IDACOUT (A)
99.95 99.90 99.85 99.80 99.75 0.5
IDACOUT (A)
0
1
2
3 VDACOUT (V)
4
IDACOUT AC Supply Rejection at Full Scale, VCC = 3V DC
20 TA = 25C 10
IDACOUT/VCC (A/V)
15
DAC ZSE (nA)
DNL (LSB)
10
5
0
1
100 10 FREQUENCY (kHz)
4
UW
1840 G01
Supply Current vs Temperature (VCC = 3V)
100.10
IDACOUT Full Scale vs VCC, VDACOUT = 1.1V
TA = 25C
430 420 410
100.00
99.95 400 390 -50 99.90 2.5
6.5
-25
0 25 50 TEMPERATURE (C)
75
100
1840 G02
3.5
4.5 VCC (V)
5.5
6.5
1840 G03
100.10 100.05 100.00
IDACOUT FS vs VDACOUT at VCC = 3V
100.5
IDACOUT FS vs VDACOUT at VCC = 5V
TA = 25C 100.3 100.1 99.9 99.7 99.5 99.3 99.1
TA = 25C
5
6
1840 G04
1.5
2.5 VDACOUT (V)
3.5
4.5
1840 G05
0
1
2
3 4 VDACOUT (V)
5
6
1840 G06
DAC Zero Scale Error at VCC = 3V, VDACOUT = 1.1V
0.2
DAC DNL vs Code at VCC = 3V
TA = 25C
0.1
5
0
-0.1
1000
1840 G07
0 -50 -25
-0.2
50 25 75 0 TEMPERATURE (C)
100
125
1 CODE
255
1840 G09
1840 G08
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LTC1840 TYPICAL PERFOR A CE CHARACTERISTICS
DAC INL at VCC = 3V
0.4 TA = 25C 0.3 BLASTB THRESHOLD (V)
BEST FIT INL (LSB)
0.2 0.1 0 -0.1
-0.2
0 CODE
PI FU CTIO S
SCL (Pin 1): Serial Clock Input. The 2-wire bus master device clocks this pin at a frequency between 0kHz and 100kHz to enable serial bus communications. Data at the SDA pin is shifted in or out on rising SCL edges. SCL has a logic threshold of 1V and an external pull-up resistor or current source is normally required. SDA (Pin 2): Serial Data Input. This is a bidirectional data pin which normally has an external pull-up resistor or current source and can be pulled down by the open drain device on the LTC1840 or by external devices. The master controls SDA during addressing, the writing of data, and read acknowledgment, while the LTC1840 controls SDA when data is being read back and during write acknowledgment. SDA data is shifted in or out on rising SCL edges. SDA has a logic threshold of 1V. A1 (Pin 3): Three State Address Programming Input. This pin can cause three different logic states internally, depending upon whether it is pulled to supply, pulled to ground, or not connected (NC). Combined with the A0 pin, this provides for nine different possible two-wire bus addresses for the LTC1840 (see Table 1). A0 (Pin 4): Three State Address Programming Input. See A1. FAULT (Pin 5): Fault Indicator Pull-Down Output. This pin has an open drain pull-down that is used to signal various fault conditions on the LTC1840. An external 10k pull-up is recommended. GPIO1, GPIO2, GPIO3, GPIO4 (Pins 6, 7, 9, 10): General Purpose Inputs/Outputs. These pins can be used as digital inputs with CMOS logic thresholds or digital outputs/LED drivers with open drain pull-downs that can be programmed to blink. GPIO pins can be programmed to produce faults due to changes in their logic states, and these faults can only be cleared by software or powering the LTC1840 down. All GPIOs default to nonfaulting logic inputs upon power-up and their functionality is changed through the serial interface. GND (Pin 8): Ground. Connect to analog ground plane. TACHA (Pin 11): Tachometer Input A. This pin is a digital input that is designed to interface to the tachometer output from a 3-wire fan. Internal logic counts between rising TACHA edges at serially programmable frequencies of 25kHz, 12.5kHz, 6.25kHz or 3.125kHz and the most recently completed count is stored in a register accessible through the serial interface. The maximum count is 255 and the LTC1840 is programmable to produce faults when a count exceeds this number. This pin has CMOS thresholds and the default conditions are to count at 3.125kHz and to not produce faults. TACHB (Pin 12): Tachometer Input B. See TACHA
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BLAST Falling Threshold at VCC = 3V
1.011 1.010 1.009 1.008 1.007 1.006 1.005 1.004 1.003
255
1840 G10
1.002 -50
-25
0 25 50 TEMPERATURE (C)
75
100
1840 G11
U
U
U
5
LTC1840
PI FU CTIO S
BLAST (Pin 13): Blast/Timer Function Input. This is a multifunction digital input pin that controls blast and timer operation. If this pin is in a logic high state at power-up or is transitioned from high to low, it will "blast" the current DAC outputs to full scale (100A) no matter what their previous state was and set a fault condition. In addition, if BLAST is in a logic high state, the serial access timer is active; this circuit measures time between serial communications to the LTC1840 and forces a blast and trips a fault if the part hasn't been accessed for about 1.5 minutes. This pin has a 1V logic threshold. IDACOUTB (Pin 14): Current DAC Output B. This is a high impedance output with a sinking current output of 0A to 100A. This current can be programmed to one of 256 values through the serial interface or it can be "blasted" immediately to full scale using the BLAST pin or by the serial access timer if it is enabled and the LTC1840 is not accessed for about 1.5 minutes. This pin will maintain the programmed current to a very tight tolerance from as low as 1.1V to at least 0.75V above VCC. The current DAC is guaranteed to be monotonic over its full 8-bit range. IDACOUTA (Pin 15): Current DAC Output A. See IDACOUTB VCC (Pin 16): Positive Supply. This pin must be closely decoupled to ground (pin 8). A 10F tantalum and a 0.1F ceramic capacitor in parallel are recommended.
BLOCK DIAGRA
SCL
1 SERIAL INTERFACE GPI/O INTERFACE 7 GPIO2
SDA
2 8-BIT COUNTER
A1 A0
3 REF 4 8 OSC
TI I G DIAGRA
SDA
tLOW SCL thD, STA tr START CONDITION tHIGH tf
6
W
W
U
U
UW
U
IDACOUTA IDACOUTB 15 I 8-BIT IDACs 14 I
FAULT 5
BLAST 13
FAULT DETECT
6 GPIO1
9 GPIO3
/ 2, 4, 8, 16
8-BIT COUNTER
10 GPIO4
GND
12 TACHB
11 TACHA
1840 BD
tsu, DAT thD, DAT
tsu, STA thD, STA tsu, STO
tBUF
1840 TD01
REPEATED START CONDITION
STOP CONDITION
START CONDITION
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LTC1840
OPERATIO
SDA
SCL S START CONDITION
Serial Interface * Simple 2-wire interface * Multiple devices on same bus * Idle bus must have SDA and SCL lines high * LTC1840 is read/write * Master controls bus * Devices listen for unique address that precedes data The START and STOP Conditions When the bus is not in use, both SCL and SDA must be high. A bus master signals the beginning of a transmission with a START condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission. Acknowledge The acknowledge signal is used for handshaking between the master and the slave. An acknowledge (LOW active) generated by the slave lets the master know that the latest byte of information was received. The acknowledgerelated clock pulse is generated by the master. The transmitter master releases the SDA line (HIGH) during the acknowledge clock pulse. The slave receiver must pull down the SDA line during the acknowledge clock pulse so
1 START 7 1 1 1 B4 B3 B2 B1 SLAVE ADDRESS 1 WR 0 1 ACK S 0 8
1 START
U
Typical 2-Wire Serial I2C or SMBus Transmission
1-7 8 9 1-7 8 9 1-7 8 9 P ADDRESS R/W ACK DATA ACK DATA ACK STOP CONDITION
1840 TD02
that it remains stable LOW during the HIGH period of this clock pulse. When a slave receiver doesn't acknowledge the slave address (for example, it's unable to receive because it's performing some real-time function), the data line must be left HIGH by the slave. The master can then generate a STOP condition to abort the transfer. If a slave receiver acknowledges the slave address, but some time later in the transfer cannot receive any more data bytes, the master must again abort the transfer. This is indicated by the slave generating the "not acknowledge" on the first byte to follow. The slave leaves the data line HIGH and the master generates the STOP condition. Commands Supported The LTC1840 supports read byte, write byte, read word (the second data byte will be all ones) and write word (the second data byte will be ignored) commands. Data Transfer Timing for Write Commands In order to help assure that bad data is not written into the LTC1840, data from a write command is only stored after a valid acknowledge has been performed. The part will detect that SDA is low on the rising edge of SCL that marks the end of the period in which the LTC1840 acknowledges the data write and then latch the data during the following SCL low period.
1 ACK S 0 8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE 1 ACK S 0 1 STOP
LTC1840 Write Byte Protocol
X X X X X R2 R1 R0 REGISTER ADDRESS
LTC1840 Read Byte Protocol
7 1 1 1 B4 B3 B2 B1 SLAVE ADDRESS 1 WR 0 1 ACK S 0 8 X X X X X R2 R1 R0 REGISTER ADDRESS 1 ACK S 0 1 7 1 RD 1 1 ACK S 0 8 D7 D6 D5 D4 D3 D2 D1 D0 DATA BYTE 1 ACK M 1
1840 TD03
1 STOP
START 1 1 1 B4 B3 B2 B1 SLAVE ADDRESS
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LTC1840
OPERATIO
LTC1840 Device Addressing It is possible to configure the part to operate with any one of nine separate addresses through the three state A0 and A1 pins. Table 1 shows the correspondence of addresses to the states of the pins:
Table 1. Device Addressing
LTC1840 Device Address A0 L NC NC H L H NC H L A1 NC H NC NC L H L L H B4 0 0 0 0 0 0 0 0 1 2-Wire Bus Slave Address Bits (B7,B6,B5 = 111) B3 0 0 0 0 1 1 1 1 0 B2 0 0 1 1 0 0 1 1 0 B1 0 1 0 1 0 1 0 1 0
For the A0 and A1 lines, L refers to a grounded pin, H is a pin shorted to VCC and NC is no connect. The pin voltage will be set to approximately VCC/2 when not connected. Bits B7, B6 and B5 of the address are hardwired to 111.
Table 2. LTC1840 Register Address and Contents
Register Name (R/W) FAULT STATUS DACA DACB TACHA TACHB GPIO Data GPIO Setup Register Address R2 R1 R0 000 001 010 011 100 101 110 111 D7 TACHA FLT (0) D6 TACHB FLT (0) D5 Blast (0) DIV1 (0) Bit 5 (0) Bit 5 (0) Cnt A5 (1) Cnt B5 (1) GPIO2 Pin (N/A) GPIO2 BLNK (0)
Note 1: Number in ( )signifies default bit status upon power-up.
8
U
Register Addresses and Contents Fault conditions are cleared by the action of writing to the fault register, but the data byte from the write command is not actually loaded into the register. A TACHA/B FLT (fault) bit will be high if the corresponding TACHA/B FLTEN bit in the status register has been set high and the corresponding TACHA/B counter has overflowed its maximum count of 255. These faults are latched internally and must be cleared by writing to the fault register or by setting TACHA/B FLTEN low. The fault will be reasserted if the counter is still in overflow after a write to the fault register. The TACH FLT bits power-up in the low state. The blast and timer bits become high after blasting and serial access time-out events, respectively. A high GPIOX FLT bit reflects that the GPIOX pin has caused a fault condition; to do so, the pin must be enabled as fault producing in the GPIO setup register (GPIOX FLTEN set high) and the logic state of the pin must change after the enable. The fault is latched internally and must be cleared through software by writing to the fault register or by setting GPIOX FLTEN low; a change in the state of the GPIOX pin from its state at the point of the fault register being written will cause another fault to be signalled.
Data Byte D4 Timer (0) DIV0 (0) Bit 4 (0) Bit 4 (0) Cnt A4 (1) Cnt B4 (1) GPIO1 Pin (N/A) GPIO1 BLNK (0) D3 GPI04 FLT (0) *See Note 2 (0/1) Bit 3 (0) Bit 3 (0) Cnt A3 (1) Cnt B3 (1) GPIO4 Reg (1) D2 GPI03 FLT (0) (0) Bit 2 (0) Bit 2 (0) Cnt A2 (1) Cnt B2 (1) GPIO3 Reg (1) D1 GPI02 FLT (0) (0) Bit 1 (0) Bit 1 (0) Cnt A1 (1) Cnt B1 (1) GPIO2 Reg (1) D0 GPI01 FLT (0) (1) LSB (0) LSB (0) Cnt A0 (1) Cnt B0 (1) GPIO1 Reg (1) TACHA FLTEN TACHB FLTEN (0) (0) MSB (0) MSB (0) Cnt A7 (1) Cnt B7 (1) GPIO4 Pin (N/A) GPIO4 BLNK (0) Bit 6 (0) Bit 6 (0) Cnt A6 (1) Cnt B6 (1) GPIO3 Pin (N/A) GPIO3 BLNK (0) GPIO4 FLTEN GPIO3 FLTEN GPIO2 FLTEN GPIO1 FLTEN (0) (0) (0) (0)
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Note 2: State of bit depends on slave address used.
LTC1840
OPERATIO
DIV1 and DIV0 program the ratio by which the internal 50kHz oscillator frequency is divided down to produce the tachometer clocks (2, 4, 8, or 16). The DIV bits power-up low, which corresponds to a frequency division of 16. For example, if DIV1 and DIV0 are both high, the divide ratio is set to 2. If DIV1 is high and DIV0 is low, the divide ratio is set to 4. If DIV1 is low and DIV0 is high, the divide ratio is set to 8. The TACHA and TACHB registers will be set to all ones by a UVLO condition. The tach counters count between rising edges on the TACHA and TACHB pins. If a counter overflows its maximum count of 255, the latch holding the count results is immediately set to 255 without waiting for the next edge on its TACH pin. This is done so that a suddenly stopped or locked rotor will be easily detectable by reading its corresponding tach register; otherwise, the register would merely hold the previous count and be waiting for a tach signal edge that isn't coming to update the overflow count. The GPIOX pin bits in the GPIO data register reflect the logic state of the pin itself, while the GPIOX register bits reflect the data that is stored in the register that controls the gate of the internal pull-down for the pin. The logic polarities of the GPIOX bits are the same as those of the GPIOX pins assuming an appropriately sized pull-up resistor (for example, a 1 value for the GPIO1 register bit will force the internal N-channel MOSFET pull-down to an offstate, resulting in a 1 value at the GPIO1 pin). For a GPIO to be used as a digital input, the GPIOX register bit is set high, which turns off the internal pull-down N-channel MOSFET, and the state of the pin can be controlled externally and read back via the GPIOX pin bit. The GPIO register bits power-up in the high state. The GPIOX BLNK bits in the GPIO setup register control whether the internal pull-down on a GPIO shuts on and off at about 1.5Hz when the GPIOX register bit is low, and the GPIOX FLTEN bits control whether a GPIO pin can trigger a fault condition by a change in state. The GPIO FLTEN and GPIO BLNK bits power-up in the low state. Serial Interface Example In this example, an LTC1840 has both address pins open (NC) and the output current of DACA will be programmed to half of full-scale (50A current sink).
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Provide a start condition on the bus by pulling SDA from high to low while SCL is high and then write the SDA bit stream 1110010 to the part for the LTC1840 slave address, followed by a 0 to indicate that a write operation will follow. All SDA transitions must happen when SCL is low, or a start or stop condition will be interpreted. The LTC1840 will then pull the SDA line low during the next SCL clock phase to indicate that it is responding to the communication attempt. To write to the DACA output register, write 00000010 to the LTC1840 and wait for the LTC1840 to acknowledge again on the following SCL cycle by pulling SDA low. Next, send the LTC1840 the value indicating the DACA current; writing the SDA data stream 10000000 sets the DAC to sink 50A. The LTC1840 will then acknowledge a third time by pulling SDA low for the next SCL cycle. Then the data will be written into the internal DACA register and IDACOUTA pin will sink 50A. Now generate a stop condition by forcing SDA from low to high while SCL is high. Tachometer Interface Operation It is common for fans to have tachometer outputs that produce two pulses per blade revolution. The LTC1840 provides two inputs that interface to circuits that count between rising edges on these pulses. The frequency at which the counting is done is programmable via the serial interface to 25kHz, 12.5kHz, 6.25kHz, and 3.125kHz, equivalent to divide by 2, 4, 8, and 16 operations on the internal 50kHz oscillator. The count values corresponding to these two inputs can also be read via the serial interface. The output registers storing these counts power-up to all ones, and they will also be loaded with all ones whenever a counter overflows between two rising edges to allow for the detection of a suddenly stopped rotor. The part can also be configured to produce a fault as soon as the counter overflows. However, the default state is to not produce such faults, so as to prevent unnecessary fault conditions while the fan is spinning up at start-up. Multiple fans with open drain tachometer output signals can be connected to a single LTC1840 tachometer input in a wired-OR fashion, as long as the fans are not active at the same time. If the fans happen to be spinning simultaneously, the counts in the tach registers will not be meaningful.
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LTC1840
OPERATIO
GPIO Operation
The GPIO circuits feature N-channel MOSFET open drain pull-downs that can drive LEDs and readback circuitry to allow the logic states of the GPIO pins to be accessed through the serial interface. The circuits that read the logic states of the pins have standard CMOS thresholds. The user must take care to minimize the power dissipation in the pull-downs. LEDs should have series resistors added to limit current and to limit the voltage drop across the internal pull-down if their forward drop is less than about VCC minus 0.7V. The N-channel MOSFET pull-downs can sink 10mA at 0.7V drop to drive LEDs. A series resistor is usually required to limit LED current and the LTC1840 internal power dissipation. See Table 3 for resistor values.
Table 3. Recommended LED Resistor Values
LED Current (mA) 1 3 5 10 1k 270 120 30 Recommended Series Resistor () VCC = 3V VCC = 5V 3k 910 510 240
Note: LED forward voltage drop assumed to be 2V.
FAULT Operation Normally, the FAULT pin internal pull-down is only enabled if one of the fault bits in the fault register is high. But it is also enabled if the part is shut down by the POR block due to low VCC supply. This POR fault does not have a corresponding fault register bit. BLAST and Serial Interface Watchdog Timer Operation The BLAST pin is used to force the DAC output currents to full value instantaneously and also to gate the operation of the serial interface watchdog timer. A blast will occur if the BLAST pin is high when the part comes out of POR or if there is a high to low transition on BLAST after POR. The threshold of the BLAST pin is about 1V, independent of VCC. The serial interface watchdog timer, which will signal a fault condition if the part has not been addressed via the serial interface for about a minute and a half, is only active
10
U
if the BLAST pin is high. If neither blasts nor an active serial interface watchdog timer are desired, this pin should be tied to ground. If timer operation is desired without having a blast occur at power-up, the pin should be pulled above 1V after the part's supply has ramped up. The blast state is cleared by writing to the fault register. Current Output DAC Interface to Switching Regulator The output of a current DAC is used to control the output voltage of a switching regulator that powers a fan, which determines the rotational speed of the fan. The resistor divider from the output of the regulator to the feedback pin to ground should be ratioed to give the minimum desired voltage from the fan, which corresponds to the minimum fan speed. The size of the resistor from the output to the feedback pin is then chosen by dividing the difference between the maximum and minimum desired fan voltages by the nominal maximum current output of the DAC, which is 100A. The value of the resistor from the feedback pin to ground is then derived from the divider ratio and the resistor value just calculated. For example, if the feedback pin of the regulator is at 1.25V with respect to ground and the minimum desired fan voltage is 5V, the top resistor in the divider should be (5V - 1.25V)/1.25V = 3 times larger than the resistor from the feedback node to ground. If the maximum desired fan voltage is 12V, the top resistor value is then (12V - 5V)/ 100A = 69.8k, and the bottom resistor is 69.8k/3 = 23.2k. See Figure 1. If the feedback pin voltage of a regulator is lower than the 1.1V compliance voltage of either of the LTC1840's current output DACs, the resistor from the regulator output to the feedback pin can be divided into two resistors, giving the DAC more room to operate. See Figure 2. If more than one fan is controlled by one regulator output, small differences in the actual rotational speeds of the fans may result in audible beat frequencies, which can be very annoying. To avoid this problem, the actual voltages applied to the fans can be varied by adding resistors or diodes in series with some of the fans, resulting in larger differences between their rotational speeds and less noticeable beating. See Figure 3.
1840f
LTC1840
OPERATIO U
VOUT (5V TO 12V) R1 69.8k IDAC LTC1840*
1.3V VFB 0.8V R1 10k R2 15k VOUT (5V TO 12V) R3 69.8k IDAC LTC1840*
VFB REGULATOR 1.25V FB
IDACOUTA 15(14) (IDACOUTB)
REGULATOR FB
IDACOUTA 15(14) (IDACOUTB)
R2 23.2k
1840 F01
1840 F02
*ADDITIONAL DETAILS OMITTED FOR CLARITY
*ADDITIONAL DETAILS OMITTED FOR CLARITY
Figure 1. Feedback Divider for 1.25V Reference
VOUT BYS10-25
Figure 2. Feedback Divider for 0.8V Reference
FAN 1
FAN 2
1840 F03
FAN 1, FAN 2: NMB 6820PL-04W-B49-D50
Figure 3. Series Diode to Avoid Beat Frequencies
PACKAGE DESCRIPTIO
0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270)
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
U
GN Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1641)
0.189 - 0.196* (4.801 - 4.978) 16 15 14 13 12 11 10 9 0.009 (0.229) REF 0.229 - 0.244 (5.817 - 6.198) 0.150 - 0.157** (3.810 - 3.988) 1 0.015 0.004 x 45 (0.38 0.10) 0 - 8 TYP 0.053 - 0.068 (1.351 - 1.727) 23 4 56 7 8 0.004 - 0.0098 (0.102 - 0.249) 0.008 - 0.012 (0.203 - 0.305) 0.0250 (0.635) BSC
GN16 (SSOP) 1098
1840f
11
LTC1840
TYPICAL APPLICATIO
12V
L1 = SUMIDA CDRH125-15OMC CIN, COUT, = PANASONIC EEV-FC1C471P R1, R2 = 1% METAL FILM
10k IN4148 TN0205A 10k CC1B 470pF
3.3V
SCL SDA 10k 130 FAULT LED1 3.3V NC NC
LTC1840 1 16 VCC SCL 2 3 4 5 6 SDA A1 A0 FAULT GPIO1 GPIO2 GND IDACOUTA IDACOUTB 15 14
0.1F
+
10F
13 SYSTEM BLAST RESET 12 TACHB TACHA GPIO4 GPIO3 11 10 9
10k
-A-
7 8
ADDRESS = 1110010 (8 OTHERS POSSIBLE) TO AUTOMATICALLY MUX TACHB BETWEEN THE TWO PARALLEL FANS, SET GPIO2 TO BLINK
RELATED PARTS
PART NUMBER LTC1625 LTC1695 LTC1694/LTC1694-1 LTC1771 LTC4300-1 DESCRIPTION No RSENSE Current Mode Synchronous Step-Down Switching Regulator SMBus/I2C Fan Speed Controller in ThinSOTTM SMBus Accelerator Ultralow Supply Current Step-Down DC/DC Controller Hot Swappable 2-Wire Bus Buffer
TM
No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 q FAX: (408) 434-0507
q
U
Controlling Fan Pair with Automatic Blast Redundancy and Fan Pair with Automatic Tach Muxing
+
CIN1B 470F
+
CIN2B 470F 1 2 3 4 5 CC2B 220pF 6 7
LTC1625 16 EXTVCC VIN SYNC RUN/SS FCB ITH SGND VOSENSE VPROG TK SW TG B00ST INTVCC BG PGND 15 14 13
4.7k CVINB 0.1F Si4410DY L1B 15H CBB, 0.22F TP0101TS (4.5V TO 12V) 3.3V
12 MBRS140T3 11 10 9 CMDSH-3 Si4410DY CVCCB 4.7F R2B 27k R1B 75k DC FAN DC FAN TACH OUT TACH OUT 2- NMB 5910PL-04W-B59-D50 FANS 2.1A NOM AT 12V 10k 10k
+
CF1B 100pF
8
+
COUT1B 470F x2
3.3V
+
CIN1 470F
+
CIN2 470F 1 2 3 4
10k LTC1625 16 EXTVCC VIN SYNC RUN/SS FCB ITH SGND VOSENSE VPROG TK SW TG B00ST INTVCC BG PGND 15 14 13 CB, 0.22F 12 MBRS140T3 11 10 9 CMDSH-3 Si4410DY CVCC 4.7F R2 27k R1 75k 4.7k CVIN 0.1F Si4410DY L1 15H (4.5V TO 12V) -A-
10k CC1 470pF
5 CC2 220pF 6 7
BYS10-25 COUT1 + 470F x2 DC FAN TACH OUT DC FAN
CF1 100pF
8
+
TACH OUT
2- NMB 5920PL-04W-B29-D50 FANS 2.2A NOM AT 12V
1840 TA03
COMMENTS Up to 97% Efficiency; 1.19V VIN 36V; 1.19V VOUT VIN; Up to 99% Duty Cycle 0.75 PMOS Linear Regulator with 180mA Output Current Rating Includes DC and AC Pull-Up Current/AC Pull-Up Current Only 10A Supply Current; 93% Efficiency; 1.23V VOUT 18V; 2.8V VIN 20V; Up to 100% Duty Cycle Prevents SDA, SCL Corruption During Live Insertion; Bidirectional Bus Buffer; Isolates Backplane and Card Capacitance
1840f LT/TP 0402 2K * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2001

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